1. Field of the Invention
The present invention relates generally to the field of fault tolerant memory devices. In one aspect, the present invention relates to a column redundancy method and system using off-pitch column shifting in connection with a semiconductor memory device.
2. Description of the Related Art
Computer systems are constructed of many components, typically including one or more processors that are connected to a motherboard for access to one or more memory devices, (such as RAM) and secondary storage devices (such as hard disks and optical discs). For example, FIG. 1 is a diagram illustrating a multiprocessor system 10 with multiple memories. Generally, a processor 1a connects to a system bus 12. Also connected to the system bus 12 is a memory (e.g., 14a). During processor operation, CPU 2 processes instructions and performs calculations. Data for the CPU operation is stored in and retrieved from memory using a memory controller 8 and cache memory, which holds recently or frequently used data or instructions for expedited retrieval by the CPU 2. Specifically, an L1 cache 4 connects to the CPU 2, followed by an L2 cache 6 connected to the L1 cache 4. The CPU 2 transfers information to the L2 cache 6 via the L1 cache 4. Memory devices (e.g., L1 cache 4, L2 cache 6, main memory 14a) in computer systems are used to store data and/or instructions, and are typically implemented in the form of integrated circuit chips. As memory size, density and complexity increase, there are more opportunities for physical and circuit defects in the constructed integrated circuits, which can lower the production yield of semiconductor devices.
Redundancy circuits are used to overcome such defects and thereby boost semiconductor yield. Various redundancy schemes have been developed to repair memories having faulty memory cells by replacing the column having the defect with a redundant column of the memory array while preserving the original addresses of the affected data paths. In general, once the location of a defective memory cell or cells is identified during testing, the column containing the defective cell(s) is effectively disabled so that it can no longer be addressed, and a spare column of memory cells physically located elsewhere on the chip is programmed to be accessed by the logical address that would have accessed the defective column. Typically, information identifying a defective element is stored in latches or fuses located on each column or row of data path, though this requires excessive space in the valuable memory array area.
As microprocessors become more and more sophisticated (such as with 32-bit or 64-bit data path processors), additional problems arise, particularly when such devices use memories having multiple arrays. For example, a single redundant set of arrays cannot compensate for a short defect between arrays belonging to two adjacent main memory arrays. Therefore, at least two sets of redundant arrays would be needed to correct such defects. Additionally, data transmissions along the redundant path can suffer a speed penalty due to the extra line length and the incidence of higher parasitic capacitance. In some instances, the input and output data path to the redundant element may be tripled in length (as compared to the primary storage element) for a wide-word computing device. Variable delays from data paths are highly undesirable in high-performance memory storage, as they force the performance of an entire memory array to be no better than that of the extended length path's performance. Finally, fuses must be laid out integrally to each set so as to be able to selectively disconnect sets in which defects exist.
Conventional redundancy solutions that address these issues are described in U.S. Pat. Nos. 5,537,665 and 5,204,836, which are hereby incorporated by reference in their entirety as if fully set forth herein. These references disclose using “on pitch” shift circuits to shift around defective memory elements. For large multi-array memories using such “on-pitch” shift circuits to shift around defective columns, the number of registers and shift circuits required to store and route redundancy information increases dramatically. In addition, an increase in the number of registers increases the tracks that need to be allocated for routing the wires carrying the redundant information. An increase in the register count creates other problems, including reduced array efficiency, reduced redundancy register yield and cosmic ray protection issues. Thus, there is a need for a scheme which minimizes register count while maintaining redundancy coverage. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.